In development process of an integrated circuit (IC), it is desirable to ensure that the hardware works correctly in the expected operating space before the IC is shipped in volume. Generally, the use of debug circuits and processes are well known in art to assist in the testing of ICs. U.S. Patent Publication No. 2012/0151263 A1 describes various embodiments of debug circuits and processes.
One challenge is to do a thorough job so that ICs are not deployed in the field, and then significant problems are subsequently discovered (e.g., by an original equipment manufacturer (OEM)). However, this is not always possible. One reason is that insufficient time may be available for cycling the hardware through the entire validation space. Another reason is that certain aspects of the hardware and state machine functionality are opaque (i.e., not easily observable).
For power saving and other purposes, some hardware circuits may be designed to be selectively powered down and/or powered off. Such circuits present additional issues in the testing of ICs.